Bane Vasić
Professor of Electrical and Computer Engineering
Professor of Mathematics
Professor, Applied Mathematics - GIDP
Professor, BIO5 Institute
Bane Vasić is a professor of electrical and computer engineering and mathematics at the University of Arizona and a director of the Error Correction Laboratory. He is one of the inventors of the soft error-event decoding algorithm, and the key architect of a detector/decoder for Bell Labs' data storage read-channel chips regarded as the best in industry.
His pioneering work on structured low-density parity check (LDPC) error correcting codes based on combinatorial designs has enabled low-complexity iterative decoder implementations. Structured LDPC codes are today adopted in a number of communications standards and data storage systems and are a prime candidate for quantum error correction. Dr. Vasić’ work on codes on graphs, trapping sets and error floor of iterative decoding algorithms has led to decoders for the binary symmetric channel with best error-floor performance known today.
He is a founder of Codelucida, a company developing advanced error correction solutions for flash memories. He is an IEEE Fellow, Fulbright Scholar, da Vinci Fellow, and a past Chair of IEEE Data Storage Technical Committee.